Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective
Chandana Anguru, Vamsi Krishna Aryasomayajula, Venkata Ramakrishna Kotha, Sresta Valasa, Sunitha Bhukya, Narendar Vadthiya, V. Bheemudu, Kallepelli Sagar, Satish Maheshwaram, Praveen Kumar Mudidhe
Abstract
This manuscript presents a performance analysis of 3-stack JL-NWFETs with different spacer materials and spacer lengths. The DC and analog/RF performance is analysed at the device level, and circuit level. In single-k spacer analysis, TiO 2 exhibits lowest I OFF of ∼89.28%, and largest I ON /I OFF ratio with better subthreshold performance of ∼42.51% as compared to Air spacer at L ext = 7 nm. In addition, TiO 2 spacer is suitable for analog applications while Air spacer for RF applications. The dual-k spacer analysis is also performed and the TiO 2 +Air spacer showed prodigious DC/Analog/RF performances dominating all other combinations. Further investigations into inner high-k spacer analysis (L sp,hk ) revealed that higher L sp,hk is suitable for DC and Analog applications whereas lower L sp,hk for RF applications. The CS amplifier designed for configurations of L sp,hk showed better gain for higher L sp,hk with the amplification gain of ∼4.8 V/V. Overall, this analysis serves as a beacon, guiding the future of JL-NWFET design for spellbinding nano-electronic devices at sub-5nm technology node.