Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
R. Ritzenthaler, Hans Mertens, Geert Eneman, E. Simoen, E. Bury, Pierre Eyben, F. M. Bufler, Yusuke Oniki, B. Briggs, Boon Teik Chan, Andriy Hikavyy, G. Mannaert, Bertrand Parvais, Adrian Chasin, Jérôme Mitard, E. Dentoni Litta, Srikanth Samavedam, Naoto Horiguchi
Abstract
Forksheet devices have been recently proposed to further reduce the n-to-p spacing/footprint of transistors on wafer. In this work, we report on a systematic comparison of DC performance of Forksheets and Nanosheets transistors (with relevant dimensions of 23nm width and 7nm thickness) co-integrated on the same wafers. It is shown that the short channel control and transport properties (from Room Temperature up to 125°C) are comparable down to LG=22nm. We also show that gate stack reliability does not suffer from the SiN deposition and etch back of the Forksheet dielectric wall process. Additionally, it is shown that both Forksheets and Nanosheets exhibit good performance for analog applications, with good intrinsic voltage gain down to short gate lengths and excellent Low Frequency Noise levels. The strain boosters options with Forksheets are also investigated by TCAD and it is shown that the average stress induced by the S/D strain boosters does not suffer from the wall presence, making Forksheets promising candidates for further transistors downscaling.