Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling
Siyong Liao, L. Yang, T.K. Chiu, Wei-Xiang You, Ting Wu, K.F. Yang, Wei‐Yen Woon, W.D. Ho, Zhidan Lin, Hao-Hsiu Hung, Jianxun Huang, Shuhua Huang, Mi‐Ching Tsai, C.L. Yu, S.H. Chen, K. K. Hu, Chih‐Cheng Shih, Y.T. Chen, Cheng‐Yi Liu, H. Y. Lin, Chih-Yuan Chung, Lijuan Su, C. Y. Chou, Yi Shen, Chia‐Ming Chang, Yuh‐Chieh Lin, M. Y. Lin, Wen‐Chin Lin, Bing‐Hung Chen, Chuanchuan Hou, F. Lai, Xudong Chen, Jay Wu, C. K. Lin, Ya-Chun Cheng, Hung-Jen Lin, Y.-C. Ku, Shiwei Lin, Leiji Lu, S. M. Jang, Min Cao
Abstract
This study establishes the groundwork for an industry-applicable, integrated nanosheet-based monolithic CFET process architecture with a gate pitch of 48nm. By introducing the middle dielectric isolation, inner spacer, and n/p source-drain isolation, the vertically stacked nFET-on-pFET nanosheet transistors yield a survival rate of over 90% and demonstrate high on-state current with low leakage, achieving a healthy six-order of magnitude on/off current ratio. This work sets the stage for further CFET development and paves the way for a practical process architecture that can fuel future logic technology scaling and PPAC advancement.