A Multiplier-Free Discrete Cosine Transform Architecture Using Approximate Full Adder and Subtractor
Elham Esmaeili, Nabiollah Shiri, Mahmood Rafiee, Ayoub Sadeghi
Abstract
A new approximate full adder (FA) and a new approximate subtractor are presented, both of them have 8 transistors, and their areas are 0.1944 μm2 and 0.1689 μm2, respectively. The FA experiences three errors, while the subtractor shows two errors. In both circuits, to improve the speed, output swing, and drivability, the gate diffusion input (GDI) and dynamic threshold (DT) techniques are implemented by carbon nanotube field effect transistor (CNTFET) technology. The FA and subtractor in order are embedded in an 8-bit ripple carry adder (RCA) and an 8-bit subtractor, then they make a new approximate multiplier-free discrete cosine transform (DCT). The 8-point approximate DCT manipulation requires only addition and no multiplication. So, computational complexity is brought down. The DCT shows power delay product (PDP), peak signal-to-noise ratio (PSNR), and a figure of merit (FoM) of 63.61 fJ, 34.96 dB, and 2.39, respectively. The features of the presented approximate DCT confirm its application for image compression and noise removal in medical images.