Lutsig: a verified Verilog compiler for verified circuit development
Andreas Lööw
Abstract
We report on a new verified Verilog compiler called Lutsig. Lutsig currently targets (a class of) FPGAs and is capable of producing technology mapped netlists for FPGAs. We have connected Lutsig to existing Verilog development tools, and in this paper we show how Lutsig, as a consequence of this connection, fits into a hardware development methodology for verified circuits in the HOL4 theorem prover. One important step in the methodology is transporting properties proved at the behavioral Verilog level down to technology mapped netlists, and Lutsig is the component in the methodology that enables such transportation.
Topics & Concepts
VerilogCompilerComputer scienceField-programmable gate arrayComputer architectureHardware description languageDevelopment (topology)Automated theorem provingElectronic circuit designComponent (thermodynamics)Embedded systemParallel computingProgramming languageCircuit designMathematicsPhysicsThermodynamicsMathematical analysisFormal Methods in VerificationPhysical Unclonable Functions (PUFs) and Hardware SecurityRadiation Effects in Electronics