A Digital Readout Integrated Circuit Based on Pixel-Level ADC Incorporating On-Chip Image Algorithm Calibration for IRFPA
Zeng Yan, Shiheng Yang, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Xiong Zhou, Yong Chen, Jun Yin, Pui‐In Mak, Qiang Li
Abstract
This article presents a digital readout integrated circuit (DROIC) with fully ON-chip image algorithm calibration based on the pixel-level 18-bit analog-to-digital converter (ADC) for infrared focal plane array (IRFPA) applications. Such ON-chip calibrations include bad pixel compensation, nonuniformity correction, and background subtraction, which are implemented to avoid ON-chip memory storage for saving power and area. The proposed DROIC was fabricated in a standard 40-nm CMOS process, and it features a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$640\times512$ </tex-math></inline-formula> array size with a 30- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> pixel pitch. The power consumption of a single-pixel ADC is less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.7 \mu \text{W}$ </tex-math></inline-formula> under a supply of 1.1 V. The data rate and the dynamic range are improved and it achieved a noise equivalent differential temperature (NEDT) of 1.8 mK and a peak signal-to-noise ratio (SNR) of 90.1 dB. A test comparison exhibits that the image quality is improved significantly when the calibration is enabled. It is the highest integration level reported DROIC, with fully ON-chip calibration and image-quality enhancement algorithm.