An Area- and Energy-Efficient Spiking Neural Network With Spike-Time-Dependent Plasticity Realized With SRAM Processing-in-Memory Macro and On-Chip Unsupervised Learning
Shuang Liu, Junjie Wang, JingLv Zhou, S. G. Hu, Qi Yu, T. P. Chen, Yang Liu
Abstract
In this article, we present a spiking neural network (SNN) based on both SRAM processing-in-memory (PIM) macro and on-chip unsupervised learning with Spike-Time-Dependent Plasticity (STDP). Co-design of algorithm and hardware for hardware-friendly SNN and efficient STDP-based learning methodology is used to improve area and energy efficiency. The proposed macro utilizes charge sharing of capacitors to perform fully parallel Reconfigurable Multi-bit PIM Multiply-Accumulate (RMPMA) operations. A thermometer-coded Programmable High-precision PIM Threshold Generator (PHPTG) is designed to achieve low differential non-linearity (DNL) and high linearity. In the macro, each column of PIM cells and a comparator act as a neuron to accumulate membrane potential and fire spikes. A simplified Winner Takes All (WTA) mechanism is used in the proposed hardware-friendly architecture. By combining the hardware-friendly STDP algorithm as well as the parallel Word Lines (WLs) and Processing Bit Lines (PBLs), we realize unsupervised learning and recognize the Modified National Institute of Standards and Technology (MNIST) dataset. The chip for the hardware implementation was fabricated with a 55 nm CMOS process. The measurement shows that the chip achieves a learning efficiency of 0.47 nJ/pixel, with a learning energy efficiency of 70.38 TOPS/W. This work paves a pathway for the on-chip learning algorithm in PIM with lower power consumption and fewer hardware resources.