Space Vector Based Enhanced Modulation Scheme for a Reduced Switch Five-Level Inverter
Poonam Jayal, G. Bhuvaneswari
Abstract
This paper proposes a new space vector pulse width algorithm-based modulation scheme for a reduced switch fivelevel inverter topology, referred to as a ‘Transistor-Clamped H Bridge (TCHB) inverter’ in literature. This inverter topology invites attention primarily due to the considerable reduction that it offers in terms of the number of active switches used in a five-level inverter topology. It uses 15 active switches as compared to the 24 being used in a conventional five-level neutral point clamped (NPC) or cascaded H-Bridge (CHB) inverter. The proposed modulation scheme aims to enhance the performance of the TCHB inverter by offering an improved performance at lower switching frequencies, such as an output with reduced total harmonic distortion (THD) content, thereby minimizing switching losses and improving the overall inverter efficiency, paving way for its utilization for high capacity motor drive applications with huge device currents switching at a slower pace. MATLAB/Simulink based simulations and experimental results obtained from the laboratory prototype of a three-phase TCHB inverter feeding an RL load validate the efficacy of the proposed modulation scheme over the conventional carrier-based scheme. A digital signal processor (DSP) and embedded coder toolbox from MathWorks are used for simplified implementation of the space vector algorithm, while realizing the experimental prototype.