Multi-Logic Sense Amplifier (MLSA) Design for In-Memory Computing
Yen‐Jen Chang, Shih-Hsiang Chen
Abstract
The widely used Von Neumann architecture must move data between memory and the computation unit when performing operations, which causes a performance bottleneck. In-memory computing is an effective way to reduce the bottleneck; therefore, we design an in-memory Boolean computing architecture based on static random access memory (SRAM). We also propose a new multi-logic sense amplifier (MLSA) design, an improvement over conventional sense amplifiers that only perform a single logical operation, either NOR/OR or NAND/AND. Our design can generate multiple logical outputs, including OR/NOR, AND/NAND, and XOR/XNOR, with a lower compute delay, lower power consumption, and less transistor count. In the experimental results, the proposed MLSA design reduces the NAND, AND, and XNOR delay by 62%, 39%, and 30%, and it also decreases the static power consumption by 40% and dynamic power consumption in computing operations by 22% compared to the conventional sensing method.