An Ultra-Low-Noise Buck Converter for Noise-Sensitive Applications
A.B. Rad, Masoud Kargaran, Seyed Mohamad Razi Moosavi, Masoud Meghdadi, Ali Medi
Abstract
An ultra-low-noise buck converter for noise-sensitive applications is presented, which utilizes a novel pseudo average current-mode control (ACMC) with an adaptive ramp generator to decrease the baseband noise. Also, in order to suppress electromagnetic interference (EMI) and high-frequency spurs, spread spectrum and secondary filter are used, respectively. The proposed ACMC buck converter suppresses the switching frequency perturbation effect on the output voltage, and as a result in the spread spectrum condition, only a small amount of noise is added to the output voltage in the baseband frequency. For the spread spectrum with an external clock, a phase-locked loop is used, which synchronizes the internal oscillator and adapts the ramp generator slope to suppress spread spectrum baseband noise. The proposed ACMC converter achieves only 58 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu V_\mathrm{rms}$</tex-math></inline-formula> noise in 100 Hz–100 kHz frequency range. Also, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pm$</tex-math></inline-formula> 10% random spread spectrum architecture suppresses the EMI level by 11 dB while achieving only 88 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu V_\mathrm{rms}$</tex-math></inline-formula> and 156 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu V_\mathrm{rms}$</tex-math></inline-formula> noise for internal and external clock synchronization, respectively. The peak efficiency of the converter is 95% and the output voltage disturbance is 100 mV at a 2-A load step with 16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> s settling time. The proposed design is implemented on a 180-nm BCD technology occupying a 1.65×3.70 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> die size.