Critical Challenges with Copper Hybrid Bonding for Chip-to-Wafer Memory Stacking
Wei Zhou, Michael Kwon, Yingta Chiu, Huimin Guo, Bharat Bhushan, Bret Street, Kunal Parekh, Akshay Singh
Abstract
Due to nonmature wafer yield and customer demand for high-number die stacking, the chip-to-wafer stacking process with only known good die is a preferred solution to advanced memory products like high bandwidth memory (HBM). However, great challenges will arise if one wants to integrate it with the copper hybrid bonding technology. The memory wafer will be diced into individual chips where large amount particles will be generated and harm the hybrid bonding. In addition, the stacking process will take hours to complete rather than seconds as in a wafer-to-wafer bonding. Hence, the plasma lasting effect will be key to success. Finally, the bottom interface (IF) wafer is usually supported by a temporary carrier to sustain the wafer handling. The current wafer support system (WSS) for the IF wafer employs an organic glue, which substantially limits the thermal budget that the memory die stacking can go through. As a result, only a low-temperature annealing is allowed and low-temperature dielectric materials added. With those constraints, it was found that a porous bonding layer was generated along the interface. Failure analysis further pointed out that Cu creeping occurred along this porous interface, which might lead to leakage. An innovative solution was proposed in this work to replace the current organic-based WSS with a thin inorganic film, which can accommodate a much higher process temperature. The chemical mechanical planarization (CMP) process is found benefited too by displaying a much more consistent copper dishing as well as a uniform dielectric profile. With this new WSS, a satisfactory chip-to-wafer copper hybrid bonding process has been achieved.