Enhanced Synaptic Memory Window and Linearity in Planar In<sub>2</sub>Se<sub>3</sub> Ferroelectric Junctions
Yu‐Rim Jeon, Dong-Yoon Kim, Dong-Yoon Kim, Chandan Biswas, Nicholas D. Ignacio, Patrick Carmichael, Shaopeng Feng, Keji Lai, Dong‐Hwan Kim, Dong‐Hwan Kim, Deji Akinwande
Abstract
Abstract A synaptic memristor using 2D ferroelectric junctions is a promising candidate for future neuromorphic computing with ultra‐low power consumption, parallel computing, and adaptive scalable computing technologies. However, its utilization is restricted due to the limited operational voltage memory window and low on/off current (I ON/OFF ) ratio of the memristor devices. Here, it is demonstrated that synaptic operations of 2D In 2 Se 3 ferroelectric junctions in a planar memristor architecture can reach a voltage memory window as high as 16 V (±8 V) and I ON/OFF ratio of 10 8 , significantly higher than the current literature values. The power consumption is 10 −5 W at the on state, demonstrating low power usage while maintaining a large I ON/OFF ratio of 10 8 compared to other ferroelectric devices. Moreover, the developed ferroelectric junction mimicked synaptic plasticity through pulses in the pre‐synapse. The nonlinearity factors are obtained 1.25 for LTP, −0.25 for LTD, respectively. The single‐layer perceptron (SLP) and convolutional neural network (CNN) on‐chip training results in an accuracy of up to 90%, compared to the 91% in an ideal synapse device. Furthermore, the incorporation of a 3 nm thick SiO 2 interface between the α‐In 2 Se 3 and the Au electrode resulted in ultrahigh performance among other 2D ferroelectric junction devices to date.