25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm<sup>2</sup> Current Density
Jonghyun Oh, Jun-Eun Park, Young‐Ha Hwang, Deog‐Kyoon Jeong
Abstract
Individual power management is required to adjust the supply voltage of intellectual properties (IPs) for better energy efficiency in a system-on-chip design [1]. For this application, integrated digital low-dropout regulators (DLDOs) are attractive with better scalability, smaller sizes of pass gates, and wider input ranges. Recently, new DLDO architectures have been presented that remove an output-decoupling capacitor [1], [2] and regulate large load currents [3], [5] while offering high current efficiency. Event-driven DLDOs achieve fast settling time with a self-clocked structure [1] and a computational controller [5]. Moreover, a modular hybrid architecture [3] and an analog-assisted loop (AA-loop) [2], [4] exhibit outstanding performance in terms of a high PSRR, low-voltage droop, and low output ripple. However, the DLDOs do not completely evade the trade-off between the size of the output capacitor and the amount of the load transient current. In this paper, the synthesizable DLDO employing a comparator (CMP)-triggered oscillator and a droop detector is presented. High current efficiency and fast response to load variation are achieved without an output capacitor. In addition, the DLDO is fully synthesized using a script-based auto place-and-route process, with the exception of only pass gates and a 210fF on-chip capacitor for droop detection. Exploiting the benefit of the capacitor-free design and the synthesizability, this work offers high current density leading to efficient integration.