Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture
K.-Y. Hsiang, C.-Y. Liao, Jun Liu, Chun‐Yu Lin, J.-Y. Lee, Zaizhu Lou, F.-S. Chang, W.-C. Ray, Z.-X. Li, Hsien‐Cheng Tseng, C.-C. Wang, Ming-Han Liao, Tuo‐Hung Hou, M. H. Lee
Abstract
The 3D vertical ferroelectric tunneling junction (FTJ) of bilayer antiferroelectric (AFE) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {Hf}_{1-x}Zr_{x}\text{O}$ </tex-math></inline-formula> 2(HZO) and Al2O3 has been demonstrated for NAND-compatible feasibility. A bilayer-type FTJ is explored for the designs of the dielectric interlayer Al2O3 0 nm to 4 nm and the ferroelectric type, while the current mechanism is revealed. The multilevel AFE-FTJ is exhibited for both the Program and Erase operations and realizes a synaptic device. High-density emerging memory and computing-in-memory (CiM) are in high demanded for the future era and can be feasible by the proposed vertical FTJ.