PIM-trie: A Skew-resistant Trie for Processing-in-Memory
Hongbo Kang, Yiwei Zhao, Guy E. Blelloch, Laxman Dhulipala, Yan Gu, Charles McGuffey, Phillip B. Gibbons
Abstract
Memory latency and bandwidth are significant bottlenecks in designing in-memory indexes. Processing-in-memory (PIM), an emerging hardware design approach, alleviates this problem by embedding processors in memory modules, enabling low-latency memory access whose aggregated bandwidth scales linearly with the number of PIM modules. Despite recent work in balanced comparison-based indexes on PIM systems, building efficient tries for PIMs remains an open challenge due to tries' inherently unbalanced shape.
Topics & Concepts
Computer scienceParallel computingLatency (audio)SkewInterleaved memoryTrieEmbeddingMemory bandwidthHigh memoryComputer architectureRegistered memoryCAS latencyAuxiliary memoryMemory managementUniform memory accessRandom access memoryComputer hardwareSemiconductor memoryMemory controllerData structureOperating systemArtificial intelligenceTelecommunicationsAdvanced Data Storage TechnologiesParallel Computing and Optimization TechniquesAdvanced Memory and Neural Computing