A Study on the Advanced Chip to Wafer Stack for Better Thermal Dissipation of High Bandwidth Memory
Sang-Yong Lee, Jinwoo Park, Jong-Kyu Moon, Min-Suk Kim, Gyujei Lee, Kangwook Lee
Abstract
One of the technical challenges in 2.5D SiP is thermal issue increase with higher performance. In this paper, mass reflow bonding with molded underfll process for chip to wafer stacking of HBM was studied. MUF material and key process parameters were optimized, and 8Hi HBM was successfully demonstrated through MR-MUF method. PKG reliability was verified, and thermal characteristic of HBM was also evaluated. Using MR-MUF method, the maximum junction temperature of memory chips was reduced by 14°C comparing that of HBM using TC-NCF method at the same DRAM operation condition.
Topics & Concepts
Three-dimensional integrated circuitMaterials scienceDramWaferChipReliability (semiconductor)StackingElectronic engineeringThermalThermal management of electronic devices and systemsProcess (computing)OptoelectronicsComputer scienceIntegrated circuitMechanical engineeringElectrical engineeringEngineeringNuclear magnetic resonanceOperating systemPower (physics)MeteorologyQuantum mechanicsPhysics3D IC and TSV technologiesInjection Molding Process and PropertiesElectronic Packaging and Soldering Technologies