A 250 MHz-to-1.6 GHz Phase Locked Loop Design in Hybrid FinFET-Memristor Technology
Naheem Olakunle Adesina, Ashok Srivastava
Abstract
There are tremendous improvements in performance of transistor in CMOS technology by scaling down its size. However, there are various challenges, such as short channel effects (SCE), that are associated with miniaturization. FinFET technology is a promising technique to overcome these issues because it offers better electrostatic control of the channel than planar CMOS transistor as the technology scales down. In this work, we have proposed a phase locked loop (PLL) design with FinFET and memristor. The resistive and capacitive (R-C) components of loop filter are replaced with memristor and memcapacitor, respectively, in order to minimize the die area and reduce power consumption. The designed PLL produces a tuning range of 0.25 - 1.60 GHz at center frequency of 1 GHz with 2.05 mW average power consumption. The voltage-controlled oscillator (VCO), which contributes majorly to the total phase noise in phase locked loop, has a phase noise -135.2 dBc/Hz at 1 MHz offset frequency. In addition, the PLL shows high reliability with wide variations in temperature.