An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications
W. Hafez, D. Abanulo, Mahmoud H. Abdel‐Kader, An Sun, C. Auth, David F. Bahr, Vijay Balakrishnan, R. Bambery, M. Beck, Mudit Bhargava, S. Bhowmick, J. Biggs-houck, J. Birdsall, D. Caselli, H.-Y. Chang, Yao‐Feng Chang, Ranjan Chaudhuri, Sandeep Chauhan, Chien‐Ting Chen, V. Chikarmane, K. Chikkadi, T. Chu, Christopher W. Connor, R. Alba, Yangdong Deng, C. Destefano, Desinta Fahma Diana, Yun Dong, P. Elfick, T. Elko-hansen, B. Fallahazad, Y. Fang, Dheren Gala, Deepak Garg, C. Geppert, Sridhar Govindaraju, W.M. Grimm, H. Grunes, Lale Guler, Zheng Guo, Arnab Sen Gupta, M. Hattendorf, S. Havelia, Jubin Hazra, Aminul Islam, Amit Kumar Jain, S. Jaloviar, Mubasher Jamil, M. Jang, Mohammod Lutful Kabir, J. Kameswaran, Eric Karl, S. Kelgeri, A. Kennedy, Caitlin Kilroy, J. Kim, Yusung Kim, D. Krishnan, Gwanhoo Lee, Hyung-Jin Lee, Q. Li, H. Lin, A. Luk, Yongtao Luo, P. Macfarlane, Abdullah Al Mamun, K. Marla, D. Mayeri, Edward J. McKenna, A. Miah, K. Mistry, M. Mleczko, S.-M. Moon, Damiano Nardi, S. Natarajan, J. Nathawat, C. Nolph, Chris Surya Nugroho, P. Nyhus, A. Oni, P. Packan, Daewon Pak, Ayushi Paliwal, R. Pandey, Ítala Paredes, K. Park, L. Paulson, Andrew Pierre, P. S. Plekhanov, C. Prasad, R. Ramaswamy, J. Riley, Johann C. Rode, Ryan Russell, Sukyoung Ryu, Hugo Saavedra, Thomas S. Salisbury, J. Sandford, F. Shah, Kun Shang
Abstract
An advanced Intel 3 FinFET technology is presented that has been optimized to provide 10% logic scaling, a full node of performance improvement and improved reliability compared to Intel 4. Through transistor enhancements, interconnect optimization, and design co-optimizations, up to 18% performance gain at iso-power is achieved over Intel 4. Intel 3 additionally enables a 210nm high-density standard cell, 1.2V-native I/O transistors, deep N-well isolation, and long-channel analog devices to provide full-featured technology design capabilities.