415/610GHz f<sub>T</sub>/f<sub>MAX</sub> SiGe HBTs Integrated in a 45nm PDSOI BiCMOS process
Vibhor Jain, John J. Pekarik, Crystal Kenney, J. Holt, Chris Durcan, Jeffrey B. Johnson, Sudesh Saroop, Mona Nafari, Vaibhav Ruparelia, Santosh Kumar Gedela, Prateek Kumar Sharma, V. Ontalus, Shweta Khokale, Saloni Chaurasia, Venkata Vanukuru, Alvin Joseph
Abstract
High Performance (HP) SiGe HBTs integrated in a 45nm PDSOI BiCMOS process with peak $f_{T}/f_{MAX}415/610$ GHz are reported here. These are the highest f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> silicon devices demonstrated in any SOI platform. Measured $f_{T}/f_{MAX}$ at transmission line metal level for this HBT is 388/600GHz which gives significant performance benefit over CMOS in RF circuit designs. HBTs are integrated in a hybrid region on the wafer formed by removing the SOI and BOX with an epitaxial growth and planarization to form a co-planar top surface with the SOI. In addition to the HP HBTs and CMOS, the process also integrates a medium breakdown HBT with $f_{T}/BV_{CBO} =270$ GHz/5.6V and RF N/P FETs with $f_{T}/f_{MAX} =270/355$ GHz and 240/295 GHz. An early CML RO design has a gate delay of 1.76ps. Simple cascode power cells show > 23 dB gain at 70GHz and > 18 dB gain at 100GHz.