SHC: 8-bit Compact and Efficient S-Box Structure for Lightweight Cryptography
Sunil Kumar, Dilip Kumar, Hemraj Shobharam Lamkuche, Vijay Shankar Sharma, Hend Khalid Alkahtani, Muna Elsadig, Mariyam Aysha Bivi
Abstract
The AES (Advance Encryption Standard) has made the development of new block ciphers unnecessary; it is now the de facto standard for most uses of block ciphers. However, the AES is still not well-suited for very limited contexts like RFID (Radio-Frequency Identification) tags and WSN(Wireless Sensor Networks), despite recent implementation advancements. In this study, we present SHC (Simple Hybrid Cipher), a new block cipher that uses a 64-bit block length and a 128-bit key length. It offers a hardware implementation that efficiently uses limited resources, making it ideal for use as a sensor in a WSN or an RFID tag. The core function of SHC depends on S-Box-based, composite field arithmetic technology, as it consumes relatively low cost on hardware implementation while still providing sufficient security as a solid encryption algorithm. The hardware implementation of SHC-64 requires 949 LUTs; it generates a maximum operating frequency of 515.995 MHz on the Xilinx-powered Artix-7 Field Programmable Gate Array (FPGA) development board. At the same time, the National Institute of Standards and Technology (NIST) recommended standard algorithm AES consumes 3645 LUTs and generates a maximum operating frequency of 277.369 MHz. The SHC-64 cipher also shows resistance against known cryptanalytics attacks.