Dual-Gate All-Electrical Valleytronic Transistors
Shen Lai, Zhaowei Zhang, Naizhou Wang, Abdullah Rasmita, Ya Deng, Zheng Liu, Weibo Gao
Abstract
The development of integrated circuits (ICs) based on a complementary metal–oxide–semiconductor through transistor scaling has reached the technology bottleneck; thus, alternative approaches from new physical mechanisms are highly demanded. Valleytronics in two-dimensional (2D) material systems has recently emerged as a strong candidate, which utilizes the valley degree of freedom to process information for electronic applications. However, for all-electrical valleytronic transistors, very low room-temperature “valley on–off” ratios (around 10) have been reported so far, which seriously limits their practical applications. In this work, we successfully illustrated both n- and p-type valleytronic transistor performances in monolayer MoS 2 and WSe 2 devices, with measured “valley on–off” ratios improved up to 3 orders of magnitude greater compared to previous reports. Our work shows a promising way for the electrically controllable manipulation of valley degree of freedom toward practical device applications.