Improved Ferroelectric/Semiconductor Interface Properties in Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> Ferroelectric FETs by Low-Temperature Annealing
Kasidit Toprasertpong, Kento Tahara, Taichiro Fukui, Zaoyang Lin, Kouhei Watanabe, Mitsuru Takenaka, Shinichi Takagi
Abstract
Crystallization annealing is a key process for the formation of the ferroelectric phase in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based ferroelectric thin films. In this study, we systematically investigate the notable tradeoff of the annealing process, with temperature varied from 300°C to 700°C, on the Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface properties of ferroelectric FETs. While high-temperature annealing leads to improved ferroelectricity, it results in the unintentional formation of an interfacial layer and the increased interface state density. Ferroelectric FETs prepared with high annealing temperature consequently show degraded subthreshold swing, decreased memory window, and increased OFF current. Our results suggest that annealing ferroelectric FETs at temperature as low as possible for sufficient ferroelectricity, which is 400°C in this study, is an effective approach to improve the device performance of Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ferroelectric FETs.