13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration
Sung‐Yong Cho, Moon‐Chul Choi, J.-S. Baek, Donggun An, Sang-Hoon Kim, Daewoong Lee, S.C. Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-Hee Cho, Chanyong Lee, Hye‐Ran Kim, Yong-Jae Shin, Hanna Park, Sang-Yong Lee, Jonghyuk Kim, Bok-Yeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hong-Jun Jin, Youngseok Lee, Young‐Tae Kim, H.J. Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Tae-Young Oh, Changsik Yoo, Sangjoon Hwang
Abstract
GDDR memory has consistently maintained a leading position in delivering high performance: necessary for applications such as artificial intelligence, deep learning, and data centers. However, achieving an elevated I/O bandwidth, beyond the latest 27Gb/s GDDR6 [1], presents significant challenges in ensuring a sufficient I/O link budget. One solution is using multi-level pulse amplitude modulation (PAM) signaling. In the GDDR7 I/O specification, single-ended PAM3 signaling is used to achieve higher data rates as it can transfer data more than 58% faster, compared to non-return-to-zero (NRZ) signaling. Furthermore, PAM3 offers a 50% larger voltage sensing margin than PAM4, which was adopted for GDDR6X [2]. Therefore, PAM3 exhibits a higher potential for bandwidth extension, given that single-ended signaling is vulnerable to random noise and crosstalk.