Integration of Ferroelectric Hf<sub>x</sub>Zr<sub>1-x</sub>O<sub>2</sub> on Vertical III-V Nanowire Gate-All-Around FETs on Silicon
Anton E. O. Persson, Zhongyunshen Zhu, Robin Athle, Lars‐Erik Wernersson
Abstract
We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.
Topics & Concepts
FerroelectricityMaterials scienceNanowireSiliconOptoelectronicsMOSFETSilicon nanowiresNanosecondCMOSStack (abstract data type)Metal gateNanoelectronicsNanotechnologyElectrical engineeringGate oxideTransistorDielectricComputer scienceVoltageOpticsEngineeringPhysicsLaserProgramming languageFerroelectric and Negative Capacitance DevicesSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit Design