22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces
Boram Kim, Hankyu Chi, Hyeongjun Ko, Sangyeon Byeon, Sungkwon Lee, Changhyun Pyo, Seul‐Gi Kim, Byungjun Kang, Eunji Song, K. W. Na, Jinyoup Cha, Hye-Soo Kim, Shinyoung Park, Wooseok Choi, Kyunghoon Kim, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim
Abstract
Demand for high-bandwidth graphics memory is rapidly increasing for various applications such as AI, deep learning, autonomous cars, etc. To meet this demand, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{GDDR}6\mathrm{X}$</tex> uses multilevel signaling (PAM4) for the first time in DRAM [1], while GDDR7 targets data-rates <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$28\text{Gb}/\mathrm{s}$</tex> or higher using PAM3 signaling. However, the increased data rate incurs higher inter-symbol interference (ISI), while PAM3 is more vulnerable to ISI than PAM2 signaling. Decision feedback equalizers (DFEs) are widely used in receivers (RX) to remove post-cursor ISI without amplifying noise. A PAM3 RX, with an analog DFE, typically employs a direct feedback (DF) implementation, which must meet stringent feedback timing requirements. As the target speed increases it is challenging to reduce the feedback time to within 1 unit interval (UI) for a PAM3 RX due to the increased line parasitics and gate loading. While the loop-unrolled (LU) DFE technique mitigates feedback timing constraints, implementing a PAM3 LU DFE results in additional area and power overhead. In view of these drawbacks, this paper proposes a new type of PAM3 DFE, which combines the qualities of DF and LU DFEs to minimize area and power overhead, while also reducing the feedback time.