Highly Manufacturable, Cost-Effective, and Monolithically Stackable 4F<sup>2</sup> Single-Gated IGZO Vertical Channel Transistor (VCT) for sub-10nm DRAM
Daewon Ha, Wonsok Lee, M.H. Cho, Masayuki Terai, Sang‐Won Yoo, Hyungtak Kim, Yunsung Lee, Sunghyun Uhm, Myung Kwan Ryu, Chang Kyung Sung, Youjian Song, Kiyoung Lee, S.W. Park, Kwang‐Sik Lee, Yongsug Tak, Eunju Hwang, Joo‐Hyung Chae, Changkyun Im, Sang-Gi Byeon, MunPyo Hong, Kyoseung Sim, Won Jai Jung, Huije Ryu, Moonju Hong, S. Park, Jung O. Park, Yujin Choi, Sangmin Lee, G. Woo, Juho Lee, Dong‐Sik Kim, Bong Jin Kuh, Yu Gyun Shin, Jaihyuk Song
Abstract
For the first time, we demonstrated experimentally 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> single-gated IGZO-VCT, monolithically stacked on top of core/peripheral transistors without wafer bonding process for sub-10nm DRAM. Sufficiently low leakage current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> ) of <1 fA/cell, subthreshold swing (SS) of 164 mV/dec and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of -1.73 V at 85°C is obtained with advanced processes. In order to achieve higher on-current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> ) and positive V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> , the impacts of fabrication processes including thickness, deposition condition and post deposition treatments of IGZO channel, and its top/ bottom interfaces are investigated utilizing top-gated planar devices. By optimizing processes for gate dielectric interface, planar devices of 70 nm gate length show excellent on-off ratio of 13 order-of-magnitude at 85°C with improved N/PBTI lifetime; extremely low I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> of 2e-18 A/um, I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> of 25 uA/um at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf> -V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> = 1.0 V, and SS of 90 mV/dec with positive V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of 0.19 V. This result implies that 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> single-gated IGZO-channel VCT can be an excellent candidate to scale down a unit cell volume for high DRAM capacity, high bandwidth and low power consumption.