Jitter-Power Trade-Offs in PLLs
Behzad Razavi
Abstract
As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself.
Topics & Concepts
JitterConvertersPhase-locked loopPower (physics)Power consumptionComputer scienceElectronic engineeringSampling (signal processing)Time-to-digital converterRange (aeronautics)Clock signalEngineeringTelecommunicationsPhysicsDetectorAerospace engineeringQuantum mechanicsAdvancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignAnalog and Mixed-Signal Circuit Design