An Efficient FPGA Implementation of Cascade Integrator Comb Filter
G. Shanthi, Aruru Sai Kumar, P. Phanidra, G.Samartha Raj, N. Niharika, K. Kalyani
Abstract
Sigma-delta modulators are decimated mostly using cascaded integrated comb (CIC) filters as down samplers. The majority of the time, this filter is employed in audio applications where it improves the resolution of the audio signal being transmitted from the transmitter end and aids in improving the audio signal’s signal-to-noise ratio. When compared to other filters, the CIC filter can replace them and performs better in terms of noise cancellation. In this paper, we proposed the CIC filter which is used to transmit the audio signals, and then the signals can be decoded with high efficiency. For FPGA implementation, initially, the filter is designed in Matlab using the Simulink toolbox. Then the Verilog file for the Simulink implementation of the CIC filter is extracted using the HDL Coder library in MATLAB. Later, the Verilog file is dumped onto FPGA for analysis. Finally, the results obtained from the proposed CIC filter are comprised of high gain, more resolution, and with less area in terms of LUTs when compared to the existing method.