Double-Floating-Gate van der Waals Transistor for High-Precision Synaptic Operations
Hoyeon Cho, Donghyun Lee, Kyungmin Ko, Der‐Yuh Lin, Huimin Lee, Sangwoo Park, Beomsung Park, Byung Chul Jang, Dong‐Hyeok Lim, Joonki Suh
Abstract
Two-dimensional materials and their heterostructures have thus far been identified as leading candidates for nanoelectronics owing to the near-atom thickness, superior electrostatic control, and adjustable device architecture. These characteristics are indeed advantageous for neuro-inspired computing hardware where precise programming is strongly required. However, its successful demonstration fully utilizing all of the given benefits remains to be further developed. Herein, we present van der Waals (vdW) integrated synaptic transistors with multistacked floating gates, which are reconfigured upon surface oxidation. When compared with a conventional device structure with a single floating gate, our double-floating-gate (DFG) device exhibits better nonvolatile memory performance, including a large memory window (>100 V), high on–off current ratio (∼10 7 ), relatively long retention time (>5000 s), and satisfactory cyclic endurance (>500 cycles), all of which can be attributed to its increased charge-storage capacity and spatial redistribution. This facilitates highly effective modulation of trapped charge density with a large dynamic range. Consequently, the DFG transistor exhibits an improved weight update profile in long-term potentiation/depression synaptic behavior for nearly ideal classification accuracies of up to 96.12% (MNIST) and 81.68% (Fashion-MNIST). Our work adds a powerful option to vdW-bonded device structures for highly efficient neuromorphic computing.