High-performance Vertical Gate-All-Around Oxide Semiconductor Transistors with 6 nm ALD IGZO Channel and Scaled Contact CD down to 28 nm
Wanpeng Zhao, Wei Cui, Lu Kang, Shiheng Lu, Wenqiang Yuan, Heng Wang, Shijie Zhan, Yuqi Wang, Yibiao Yin, K. Kaneko, Lijuan Xing, Xia Sang, Yuan Shao, Zebin Lin, Hongguang Shen, Xiaojuan Cui, Ying Wu, Jeffrey Xu
Abstract
Vertical gate-all-around (GAA) indium-gallium-zinc-oxide (IGZO) FETs are demonstrated on an 8-inch platform with a thin IGZO channel of 6 nm and a short gate length of 48 nm. The device exhibits a high on-state current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{I}_{\text{ON}})$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$111.4\ \mu\mathrm{A}/\mu \mathrm{m}$</tex> @ <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{DS}}=1.5\ \mathrm{V},\ \mathrm{V}_{\text{GS}}=2\ \mathrm{V}$</tex> with scaled source/drain (SD) contact CD of 40 nm, a positive threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf>) of 0.13 V, a low SS of 75 mV/dec, and a small drain induced barrier lowering (DIBL) of 20.9 mV/V. Further scaling SD CD to 28 nm leads to a slightly drop of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{ON}}$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$95.5\ \mu\mathrm{A}/\mu \mathrm{m}$</tex>. The stability and BEOL compatibility of devices are also evaluated. Excellent bias temperature stability (BTS) is obtained with optimized gate stack, showing a small <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{TH}}$</tex> shift of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm 3\ \text{mV}$</tex> after stressing 1k seconds under <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{GS}}=\pm 2\ \mathrm{V}$</tex>. The device characteristics are well maintained with small <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{TH}}$</tex> shift of 28 mV after annealing in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{N}_{2}$</tex> at 400°C for 1 hr, indicating good stability with BEOL compatible thermal budget. Our results prove that IGZO is a promising channel material for high-density scaled BEOL transistor applications.