A Brain-Inspired ADC-Free SRAM-Based In-Memory Computing Macro With High-Precision MAC for AI Application
Zihao Xuan, Chang Liu, Yue Zhang, Yuan Li, Yi Kang
Abstract
In this brief, an ADC-free SRAM-based IMC macro is proposed, which enables energy-efficient and high-precision MAC operation by brain-inspired computing. We identify two key features that support IMC macro to achieve high energy efficiency and high precision MAC calculation. First, the temporal-coding spiking neuron circuit is used to replace the analog-to-digital converter (ADC) to achieve high-efficiency data conversion. Second, the digital adder tree logic eliminates the cost of moving partial sums between PEs and increases the parallelism of the calculations. The mixed-signal SRAM-based IMC macro is designed for processing artificial intelligence (AI) algorithms with reconfigurable precisions based on bit-wise input and weight. In an experiment, the proposed SRAM-based IMC macro with an area of 3.41 mm2 was designed in 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {\mathrm{ m}}$ </tex-math></inline-formula> CMOS technology. Post-layout simulation results indicate that the 16Kb IMC macro achieves 10.8-13.5 TOPS/W with 4-b inputs, 4-b weights, and 14-b MAC-value outputs.