Realizing On/Off Ratios over 10<sup>4</sup> for Sub-2 nm Vertical Transistors
Likuan Ma, Quanyang Tao, Yang Chen, Zheyi Lu, Liting Liu, Zhiwei Li, Donglin Lu, Yiliu Wang, Lei Liao, Yuan Liu
Abstract
Vertical transistors hold promise for the development of ultrascaled transistors. However, their on/off ratios are limited by a strong source-drain tunneling current in the off state, particularly for vertical devices with a sub-5 nm channel length. Here, we report an approach for suppressing the off-state tunneling current by designing the barrier height via a van der Waals metal contact. Via lamination of the Pt electrode on a MoS 2 vertical transistor, a high Schottky barrier is observed due to their large work function difference, thus suppressing direct tunneling currents. Meanwhile, this “low-energy” lamination process ensures an optimized metal/MoS 2 interface with minimized interface states and defects. Together, the highest on/off ratios of 5 × 10 5 and 10 4 are realized in vertical transistors with 5 and 2 nm channel lengths, respectively. Our work not only pushes the on/off ratio limit of vertical transistors but also provides a general rule for reducing short-channel effects in ultrascaled devices.