The Impacts of Ferroelectric and Interfacial Layer Thicknesses on Ferroelectric FET Design
Nujhat Tasneem, Muhammad Mainul Islam, Zheng Wang, Hang Chen, Jae Hur, Dina H. Triyoso, Steven Consiglio, Kandabara Tapily, Robert D. Clark, Gert J. Leusink, Shimeng Yu, Winston Chern, Asif Islam Khan
Abstract
Despite tremendous interests in ferroelectric field-effect transistors (FEFETs) for embedded, data-centric applications, the fundamental trade-offs between memory window (MW) and write voltage to optimize performance remains poorly understood. To that end, we fabricated ferroelectric (FE) ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> based, p-type FEFETs and studied the impacts of FE and the interfacial oxide layer (IL) thicknesses ( t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> and t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IL</sub> , respectively) on device performance. We observe that a decrease of t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> and t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IL</sub> reduces not only write voltages for erasing and programming, but also the memory window. A quantitative analysis of these results offers the following insights and guidelines for FEFET design: to decrease write voltages, all of t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> , t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IL</sub> and coercive field of FE needs to decrease, and to compensate for the subsequent decrease in MW, the polarization of the FE needs to be increased - notwithstanding the fact that the reliability implications of the magnitude of FE polarization still need to be understood.