High Peformance 3D Flash Memory with 3.2Gbps Interface and 205MB/s Program Throughput based on CBA(CMOS Directly Bonded to Array) Technology
Shotai Kobayashi, Ken Tashiro, Yoshiki Minemura, K Nakagami, K. Arita, T. Oohashi, Keita Funayama, Hiroshi Sakai, M. Mushiga, Kohki Okabe, Yoshinori Kanno, S. Shimizu, Emi Fujikura, Aya Nakae, Koichi Yamaguchi, Hideki Yamawaki, Kanako Nakajima, Munetake SATO
Abstract
We report the advantages of using CMOS directly bonded to array (CBA) technology in 3D flash memory. Improvements in interface speed, operation latency, and memory cell reliability are explored based on experimental and simulated data from 218-word-line (WL) stacked structures. The improvement derived from CBA enables BiCS FLASH™ generation 8 to operate with a high interface speed of 3.2Gbps and a high program throughput of 205MB/s with 3 bits per memory cell. A chip architecture to achieve well-scaled bit density of more than 18Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the world's highest in the 2xx- WL (about 218-232 WL) node, is also discussed.