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A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training

Sangsu Jeong, Jeongwoo Park, Dongsuk Jeon

2022ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)25 citationsDOI

Abstract

This paper presents a digital compute-in-memory (CIM) macro for accelerating deep neural networks. The macro provides high-precision computation required for training deep neural networks and running state-of-the-art models by supporting floating-point MAC operations. Additionally, the design supports variable computation precision, enabling optimized processing for different models and tasks. The design achieves 1.644TFLOPS/W energy efficiency and 57.9GFLOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> computation density while supporting a wide range of floating-point data formats and computation precisions.

Topics & Concepts

ComputationComputer scienceFloating pointArtificial neural networkMacroStatic random-access memoryInferenceVariable (mathematics)Computer engineeringPoint (geometry)Artificial intelligenceRange (aeronautics)Parallel computingAlgorithmComputer hardwareMathematicsEngineeringProgramming languageGeometryAerospace engineeringMathematical analysisAdvanced Memory and Neural ComputingFerroelectric and Negative Capacitance DevicesParallel Computing and Optimization Techniques
A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training | Litcius