Energy and Error Analysis Framework for Approximate Computing in Mobile Applications
Chandan Kumar Jha, Sneha N. Ved, I. Vivek Anand, Joycee Mekie
Abstract
In this brief, we propose a framework that enables us to analyze energy and error for mobile applications when run on systems with approximate circuits. Approximate circuits have conventionally been used in image/video processing applications, which are mostly limited to 8-bits. To the best of our knowledge this is the first work where approximate circuits have been evaluated on a 32-bit processor running real mobile applications. We observe that in approximate adders where Carry is approximated, with 2-bit approximation in LSB, the absolute average error in image processing applications is ~ 3. However, in mobile applications approximation in Carry can lead to an overflow. Hence, approximate adders with Carry approximation are not suitable for mobile computing. We also show the role of data-dependent switching in energy consumption and highlight which input pattern should not be approximated to obtain lesser error. In this brief, we also propose design of three energy-efficient approximate hybrid CMOS full-adders with varying levels of inaccuracies. The adder designs are implemented in UMC 65-nm technology using Cadence Virtuoso. Compared to existing approximate adders, on an average, the proposed adders consume 44% lesser energy and have 2× lesser energy delay product. Our proposed adder designs have similar leakage power as compared to the existing adders.