A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW
Amy Whitcombe, Chun C. Lee, Asma Beevi Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent Carlton, Peter Sagazio, Stefano Pellerano, Christopher Hull
Abstract
Compact, high-bandwidth analog-to-digital converters (ADCs) with moderate resolution are a critical building block in high-speed communication links. In this work, a hybrid time and voltage domain ADC is presented that uses a single high-speed voltage-to-time converter (VTC) as a high-bandwidth sampling buffer for a four-way time-interleaved successive approximation (SAR) ADC. Time-domain encoding also enables a low-power 3b SAR assist time-to-digital converter (TDC) to enhance SAR speed with minimal calibration. A 0.0045 mm2 prototype fabricated in 22 nm fin field-effect transistor (FinFET) CMOS provides 13 GHz effective resolution bandwidth (ERBW) and consumes 6.0 mW with a Nyquist signal-to-noise-and-distortion ratio (SNDR) of 38 dB at 3.8 GS/s, for 24.4 fJ/step Walden FoM.