A $4.96\mu\mathrm{W}$ 15b Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC
Yuyan Liu, Menglian Zhao, Yibo Zhao, Xiaopeng Yu, Nianxiong Tan, Le Ye, Zhichao Tan
Abstract
The incremental analog-to-digital converter (IADC) is attractive in many applications, such as smart sensors and event-driven loT devices, which need ADCs with high resolution, high power efficiency, and can be multiplexed between multiple inputs. Despite these advantages, they usually need an oversampled clock. A self-timed incremental <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma$</tex> ADC is proposed in [1], which does not need any oversampled clock and has similar advantages to self-timed (or asynchronous) SAR ADCs. Since it is automatically powered down once a conversion is completed, it can adapt to a wide range of conversion rates in an energy-efficient way. However, the zero-crossing detector leads to high noise, and correlated level-shifting results in complex self-timed operation. Thus it only achieves a Schreier FoM of 157.1 dB. To increase resolution and reduce power consumption, this paper proposes an improved self-timed incremental zoom ADC. It consumes only <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.96\mu \mathrm{W}$</tex> while achieving 93dB SNR in 0.37ms conversion time, resulting in a Schreier FoM of 177.3dB. This is achieved by using an asynchronous zoom ADC structure, and a fully differential self-timed dynamic-amplifier-based integrator.