Novel Parallel-Processing-Based Hardware Implementation of Baseband Digital Predistorters for Linearizing Wideband 5G Transmitters
Hai Huang, Jingjing Xia, Slim Boumaiza
Abstract
In this article, a real-time digital predistortion (DPD) hardware architecture is presented for the linearization of fifth-generation (5G) transmitters with wideband modulation signals. To overcome the linearization bandwidth constraint imposed by the maximum clock frequency of the digital circuit, a new parallel-processing DPD engine architecture is devised to allow multiple samples to be processed per clock cycle. To minimize the complexity and power consumption of the transmitter-observation-receiver that typically scales with the linearization bandwidth, an undersampling scheme using a single low-speed ADC optimized for hardware implementation is devised. The proposed real-time DPD architecture is implemented in a commercial field-programmable gate array that achieves a scalable linearization bandwidth of up to 2.4 GHz with a 300-MHz core clock rate for the digital circuits. The linearization performance and bandwidth scalability of the proposed real-time DPD system were demonstrated experimentally using a silicon-based Doherty power amplifier with a 400-MHz wideband signal operating at 28 GHz and over-the-air measurements using a 64-element beamforming array with an 800-MHz wideband signal also at 28 GHz.