A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers
Aria Samiei, Hossein Hashemi
Abstract
We present a 180-nm CMOS bidirectional neural interface system-on-chip that enables simultaneous recording and stimulation with on-chip stimulus artifact cancelers. The front-end (FE) cancellation scheme incorporates a least-mean-squares (LMS) engine that adapts the coefficients of a two-tap infinite-impulse-response filter to replicate the stimulation artifact waveform and subtract it at the FE. Measurements demonstrate the efficacy of the canceler in mitigating artifacts up to 700 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> and reducing the FE amplifier saturation recovery time in response to a 2.5-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> artifact. Each recording channel houses a pair of adaptive infinite-impulse-response filters, which enables the cancellation of the artifacts generated by the simultaneous operation of the two on-chip stimulators. The analog FE consumes 2.5 μW of power per channel and has a maximum gain of 50 dB and a bandwidth of 9.0 kHz with 6.2- μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> integrated input-referred noise.