Probabilistic Analysis of Dynamic Power and Area in Network on Chip
G. P. Ramesh
Abstract
Abstract The power used by digital integrated circuits has become a key restriction for the design and development of VLSI as the device complexity and transistor density increase. Clock-gate synthesis methods are applied to circuits to prune changes in registers by modifying the next-state register functions in order to reduce complex power dissipations. Therefore, a sequential inspection of the circuits is needed for testing this form of synthesis. A new design to increase the efficiency of network-on-chip buffers and minimize the overall area and power consumption of the router is proposed. The non-uniform use of buffers in the network is leveraged, and control is used in unusual buffers. A part of the buffer is turned on instead of shutting down the buffer completely. For some recent studies, power-gating inactive components have been used as a promising approach to minimize static and dynamic power consumption, although its disadvantages, like wake-up delay and power overhead, should also be properly addressed. Throughout this work, a probabilistic experiment was carried out to estimate the power-gating performance and a control unit was proposed to handle the confirmation of the sleep signal to buffer entries based on the results of the study. The analysis results show an average increase in static power savings. For the research community to tackle the Contest of improved power performance and efficiency, including control gate, operating insulation, storage slicing, power gate and intensity scaling, respectively. The analysis is also examined other systems and strategies for optimization built to reduce power further without noticeable loss of performance.