A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier
Ziwei Li, Wenbin He, Fan Ye, Junyan Ren
Abstract
An energy-efficient dynamic comparator is presented and analyzed in this paper. The pre-amplifier is dynamically powered by a floating reservoir capacitor and consists of an inverter-based CMOS input pair embedded in a latch. The dynamic power source enables input common-mode voltage insensitivity and the latch-embedding reduces its delay time and power consumption. The proposed comparator is simulated in 28-nm CMOS technology. It is shown that the delay time and energy efficiency are improved then the prior floating preamplifier comparator. The maximum clock frequency reaches 1.8 GHz, consuming only 0.7 pJ per comparison while achieving 30-μV input-referred noise. The energy efficiency is increased threefold than the previous floating pre-amplifier comparator with a faster comparator decision.