A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology
F. Piro, G. Aglieri Rinella, A. Andronic, M. Antonelli, M. Aresti, Roberto Baccomi, P. Becht, S. Beolè, Justus Braach, M. D. Buckland, E. Buschmann, P. Camerini, F. Carnesecchi, L. Cecconi, Edoardo Charbon, G. Contin, D. Dannheim, Jeimmy Melo, W. Deng, A. di Mauro, Mirella Dimitrova Vassilev, S. Emiliani, Jan Anton Hasenbichler, H. Hillemanns, G. H. Hong, А. Исаков, A. Junique, Alexander Kluge, Artem Kotliarov, F. Křížek, T. Kugathasan, L. Lautner, C. Lemoine, M. Mager, D. Marras, P. Martinengo, S. Masciocchi, M. W. Menzel, Magdalena Münker, A. Rachevski, Karoliina Rebane, F. Reidt, R. Russo, I. Sanna, Valerio Sarritzu, S. Senyukov, W. Snoeys, Jory Sonneveld, M. Šuljić, P. Švihra, N. Tiltmann, G. L. Usaı́, J.B. Van Beelen, C. Vernieri, A. Villani
Abstract
This paper presents the design of a front-end circuit for monolithic active pixel sensors. The circuit operates with a sensor featuring a small, low-capacitance (< 2 fF) collection electrode and is integrated in the DPTS chip, a proof-of-principle prototype of 1.5 mm × 1.5 mm including a matrix of 32 × 32 pixels with a pitch of 15 μm. The chip is implemented in the 65 nm imaging technology from the Tower Partners Semiconductor Co. foundry and was developed in the framework of the EP-R&D program at CERN to explore this technology for particle detection. The front-end circuit has an area of 42 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and can operate with a power consumption as low as 12 nW. Measurements on the prototype relevant to the front-end will be shown to support its design.