Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style
Wanyuan Pan, Yihe Yu, Chengcheng Tang, Ningyuan Yin, Zhiyi Yu
Abstract
With the development of Very Large-Scale Integration (VLSI) technology, circuit designers are increasingly focused on achieving low power, high speed, and small area. Among various circuit components, multiplier circuits play an important role in improving the overall system performance due to their significant power consumption and impact on circuit speed. In this paper, we propose a novel 8-bit signed multiplier based on the Pass Transistor Logic (PTL) that outperforms existing designs. The post-layout simulation results show that the proposed design reduces area, delay, and power by 13.45%, 9.72%, and 15.19%, respectively, compared to the multiplier synthesized using Synopsys Design Compiler (DC). Compared to other 8-bit multipliers proposed in references, our design also shows at least a 27.66% improvement in power-delay product (PDP). Additionally, the proposed circuits exhibit superior performance at different operating voltages and process corners.