Special Session: A Call to Standardize Chip-let Interconnect Testing
Sreejit Chakravarty
Abstract
Yield considerations led to die-disaggregation. Implementing complex functions on an SoC led to functional partitioning. These trends have spurred the need for integrating heterogeneous chip-lets from multiple fab vendors, using proprietary interconnect technology. Chip-let interconnects must be thoroughly tested, post packaging, to guarantee correct SoC functionality. This paper argues for the need to standardize test requirements for chip-let interconnects and features to be incorporated into such a standard. This can be part of IEEE 1838 standard for chip-let testing.
Topics & Concepts
InterconnectionChipSession (web analytics)System on a chipComputer scienceEmbedded systemReliability engineeringComputer architectureEngineeringTelecommunicationsWorld Wide Web3D IC and TSV technologiesVLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure Analysis