On the Conduction Properties of Vertical GaN n-Channel Trench MISFETs
Eldad Bahat‐Treidel, Oliver Hilt, Veit Hoffmann, Frank Brunner, Nicole Bickel, Andreas Thies, Kornelius Tetzner, Hassan Gargouri, Christian Huber, Konstanty Donimirski, Joachim Würfl
Abstract
ON-state conductance properties of vertical GaN <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -channel trench MISFETs manufactured on different GaN substrates and having different gate trench orientations are studied up to 200 °C ambient temperature. The best performing devices, with a maximum output current above 4 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and an area specific ON-state resistance of 1.1 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , are manufactured on ammonothermal GaN substrate with the gate channel parallel to the a-plane of the GaN crystal. The scalability of the devices up to 40 mm gate periphery is investigated and demonstrated. It is found that, in addition to oxide interface traps, the semiconductor border traps in the p-GaN layer limit the available mobile channel electrons and that the channel surface roughness scattering limits the channel mobility. Both strongly depend on the gate trench orientation and on the GaN substrate defect density.