Design and Implementation of a Logistic Map-Based Pseudo-Random Number Generator on FPGA
Tee Hui Teo, Maoyang Xiang, Mostafa Elsharkawy, Hen Rin Leao, Mateo Jalen Andrew Calderon, Jun Lei Lee, Syarifuddin Azhar Bin Rosli, Hui Ying See, Eng Gee Lim
Abstract
Chaotic systems can be employed in hardware to generate pseudo-random numbers, which is essential for a wide range of applications, including cryptography, Very Large Scale Integration (VLSI) testing, gaming, and simulations. Field-Programmable Gate Arrays (FPGAs) offer a flexible platform for implementing chaotic-based random number generators, integrating real-time data handling and visualization capabilities. This work presents the design and implementation of a pseudo-random number generator (PRNG) deployed on FPGA based on the logistic map for chaotic sequence generation. The generated pseudo-random numbers are further transformed via a Central Limit Theorem (CLT) function to produce a Gaussian distribution. The system architecture integrates several FPGA modules to support real-time interaction and data visualization: a clock generator, a Universal Asynchronous Receiver-Transmitter (UART) interface, a Xilinx Analog-to-Digital Converter (XADC), and a 7-segment display driver. These components enable the display of PRNG values directly on the FPGA and the transmission of data to a laptop for histogram analysis, confirming the Gaussian characteristics of the output.