Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts
S. Demuynck, V. Vega Gonzalez, C. Cavalcante, Lucas Petersen Barbosa Lima, Karen Stiers, Chuanxiang Sheng, A. Vandooren, Maryam Hosseini, Xiuju Zhou, Hans Mertens, T. Chiarella, J. Bömmels, Roger Loo, Erik Rosseel, Clément Porret, Yosuke Shimura, Aparna Akula, G. Mannaert, S. Choudhury, Vincent Brissonneau, Emmanuel Dupuy, Tanmoy Sarkar, Nathali Franchina Vergel, A. Peter, N. Jourdan, Jean-Philippe Soulié, K. Vandersmissen, Farid Sebaai, P. Puttarame Gowda, K. Lai, A. Mingardi, Siddhartha Sarkar, Koen D’havé, Boon Teik Chan, A. Sepulveda Marquez, R. Langer, I. Gyo Koo, Efrain Altamirano Sánchez, K. Devriendt, Paulina Rincon Delgadillo, Frédéric Lazzarino, Jérôme Mitard, J. Geypen, Eva Grieten, D. Batuk, Y-F. Chen, F. Verbeek, Frank Holsteyns, S. Subramanian, Naoto Horiguchi, S. Biesemans
Abstract
This work reports on the first demonstration of monolithic CFET CMOS co-integrating Middle Dielectric Isolation (MDI), Inner Spacers (ISP) and Stacked frontside patterned Contacts. The flow results in functional CMOS devices on a common gate architecture. The MDI formation is done before source drain (SD) recess for optimal bottom junction (BJ) formation. The paper discusses the challenges of using stacked contacts to form the top device junction (TJ). Finite accuracy of bottom device contact (BC) registration from frontside results in a limited process latitude to access the top device channel for TJ formation while keeping the integrity of MDI and ISP. Top device survival rate increases from 11% to 79% by eliminating the frontside BC. We show feasibility of moving BC to the wafer backside with registration accuracy below 3nm.