Gate-Controlled LVTSCR for High-Voltage ESD Protections in Advanced CMOS Processes
Ruibo Chen, Hongxia Liu, Cong Yan, Feibo Du, Aoran Han, Yuxin Zhang, Wei Huang, Qi Xiang, Tianzhi Gao, Hao Wei, Zhiwei Liu
Abstract
In this article, a novel high robust and latch-up immune electrostatic discharge (ESD) protection device, called gate-controlled low-voltage-triggered silicon-controlled rectifier (GC-LVTSCR), is proposed for 5-V I/O protection applications in the advance 40-nm CMOS technology. By incorporating a surface current diverting path with a controlling poly-silicon gate (CG) into the conventional LVTSCR, the GC-LVTSCR’s ESD characteristics can be improved and modulated with two bias conditions of CG. The first improved GC-LVTSCR structure named gate-to-body SCR (GBSCR) with the CG tied to the PWell’s body is expected to realize higher holding voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {h}}{)}$ </tex-math></inline-formula> and lower trigger voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {t1}})$ </tex-math></inline-formula> , while the other structure named gate-to-drain SCR (GDSCR) using the CG connected to the bridging p+ region of LVTSCR is designed to gain even higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {h}}$ </tex-math></inline-formula> . Measurement results show that the GBSCR has <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 11% lowered <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {t1}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 38% enhanced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {h}}$ </tex-math></inline-formula> , and improved charged device model (CDM) characteristics by comparing with the traditional LVTSCR, and the GDSCR possesses a further improved <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {h}}$ </tex-math></inline-formula> with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 45% higher than the GBSCR. Besides, the new devices are expected to protect 5 V or above I/O in submicrometer technologies and have been realized in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD process.