Bandwidth-Enhanced Oversampling Successive Approximation Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer
Longjie Zhong, Jun Yang, Donglai Xu, Xinquan Lai
Abstract
The bandwidth-enhanced oversampling successive approximation (BE-OSA) readout technique is proposed in this article to reduce the noise floor of the readout circuit for micro-electromechanical systems (MEMS) capacitive accelerometer while achieving high power efficiency in terms of the figure of merit (FoM). The open-loop structure has been widely used in MEMS capacitive accelerometer for the Internet of Things (IoT) applications due to its low power consumption. However, in the open-loop accelerometer, the capacitance variation in the sensing element is limited to the femto-farad level to overcome nonlinearity. As a result, the thermal noise from the parasitic capacitance becomes significant. The ability of the readout circuit to deal with thermal noise is determined by the front-end switched-capacitor capacitance-to-voltage convertor (SC CVC) rather than the back-end analog-to-digital converter (ADC). To reduce the noise floor, the traditional oversampling method increases the sampling frequency of SC CVC by increasing the transconductance of the amplifier, but this leads to low power efficiency. In this work, the BE-OSA technique provides a high power efficiency method as it increases the sampling frequency of SC CVC without increasing the transconductance of the amplifier. The SC CVC based on the BE-OSA technique is demonstrated in a readout circuit fabricated by a commercial 0.18-μm Bipolar-CMOS-DMOS (BCD) process and tested with a femto-farad MEMS accelerometer. The measurement results show that compared with the readout circuit without using the BE-OSA technique, the readout circuit using BE-OSA reduces the noise floor from 2.5 to 0.9 aF/√Hz. Compared with other similar works, the proposed readout circuit achieves the best power efficiency in terms of both the absolute power efficiency (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> = 243 fJ) among the switched-capacitor readout circuits and the relative power efficiency (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> = 0.14).